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Philips Semiconductors
Product specification
Dual D-type flip-flop
74ABT74
QUICK REFERENCE DATA
SYMBOL PARAMETER Propagation delay CPn to Qn, Qn Output to Output skew Input capacitance Total supply current VI = 0V or VCC Outputs disabled; VCC = 5.5V CONDITIONS Tamb = 25C; GND = 0V TYPICAL UNIT
DESCRIPTION
The 74ABT74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock input. When set and reset are inactive (high), data at the D input is transferred to the Q and Q outputs on the low-to-high transition of the clock. Data must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output.
tPLH tPHL tOSLH tOSHL CIN ICC
CL = 50pF; VCC = 5V
3.0 2.5 0.5 3 50
ns
ns pF A
LOGIC SYMBOL (IEEE/IEC)
PIN CONFIGURATION
RD1 D0 CP0 SD1 Q0 Q0 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC RD1 D1 CP1 SD1 Q1 Q1 10 11 C2 S 9 4 3 C1 2 1 1D R 6
S
&
5
SF00045
12 13
2D R
8
PIN DESCRIPTION
PIN NUMBER 1, 2, 3, 4, 10, 11, 12, 13 5, 6, 8, 9 7 14 SYMBOL NAME AND FUNCTION
SF00047
RDn, Dn, Data inputs CPn, SDn Qn, Qn GND VCC Data outputs Ground (0V) Positive supply voltage
SD 4, 10
LOGIC DIAGRAM
LOGIC SYMBOL
2 12 RD 1, 13 5, 9 Q
D0 D1 3 4 1 11 10 13 CP0 SD0 RD0 CP1 SD1 RD1 Q0 Q0 Q1 Q1 VCC = Pin 14 GND = Pin 7 VCC = Pin 14 GND = Pin 7 D 2, 12 CP 3, 11 6, 8 Q
SF00048
5 6 9 8
SA00359
ORDERING INFORMATION
PACKAGES 14-Pin Plastic DIP 14-Pin plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74ABT74 N 74ABT74 D 74ABT74 DB 74ABT74 PW NORTH AMERICA 74ABT74 N 74ABT74 D 74ABT74 DB 74ABT74PW DH DWG NUMBER SOT27-1 SOT108-1 SOT337-1 SOT402-1
1995 Sep 22
1
853-1813 15793
Philips Semiconductors
Product specification
Dual D-type flip-flop
74ABT74
FUNCTION TABLE
INPUTS SD L H L H H H RD H L L H H H CP X X X D X X X h l X OUTPUTS Q H L H H L NC Q L H H L H NC OPERATING MODE Asynchronous set Asynchronous reset Undetermined* Load "1" Load "0" Hold NOTES: H = High voltage level h = High voltage level one setup time prior to low-to-high clock transition L = Low voltage level l = Low voltage level one setup time prior to low-to-high clock transition NC= No change from the previous setup X = Don't care = Low-to-high clock transition = Not low-to-high clock transition * = This setup is unstable and will change when either set or reset return to the high level.
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 DC output diode current DC output voltage3 VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 40 -65 to 150 UNIT V mA V mA V mA C
DC output current Storage temperature range
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 -40 PARAMETER MIN 4.5 0 2.0 0.8 -15 20 10 +85 MAX 5.5 VCC V V V V mA mA ns/V C UNIT
1995 Sep 22
2
Philips Semiconductors
Product specification
Dual D-type flip-flop
74ABT74
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C MIN VIK VOH VOL II IOFF ICEX IO ICC ICC Input clamp voltage High-level output voltage Low-level output voltage Input leakage current Power-off leakage current Output High leakage current Output current1 Quiescent supply current Additional supply current per input pin2 VCC = 4.5V; IIK = -18mA VCC = 4.5V; IOH = -15mA; VI = VIL or VIH VCC = 4.5V; IOL = 20mA; VI = VIL or VIH VCC = 5.5V; VI = GND or 5.5V VCC = 0.0V; VO or VI 4.5V VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; VI = GND or VCC VCC = 5.5V; One data input at 3.4V, other inputs at VCC or GND -50 2.5 TYP -0.9 2.9 0.35 0.01 5.0 5.0 -75 2 0.25 0.5 1.0 100 50 -180 50 500 -50 MAX -1.2 2.5 0.5 1.0 100 50 -180 50 500 Tamb = -40C to +85C MIN MAX -1.2 V V V A A A mA A A UNIT
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flop or latch after applying the power.
AC ELECTRICAL CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM MIN fMAX tPLH tPHL tPLH tPHL tOSHL tOSLH1 Maximum clock frequency Propagation delay CPn to Qn, Qn Propagation delay Sn, Rn to Qn, Qn Output to Output skew An or Bn to Yn 1 1 3 4 180 1.0 1.0 1.0 1.0 Tamb = +25C VCC = +5.0V TYP 250 3.0 2.5 3.4 2.9 0.5 4.2 3.5 4.9 4.5 0.6 MAX Tamb = -40C to +85C VCC = +5.0V 0.5V MIN 150 1.0 1.0 1.0 1.0 4.7 4.0 6.2 5.2 0.6 MAX MHz ns ns ns UNIT
NOTE: 1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH); parameter guaranteed by design.
AC SETUP REQUIREMENTS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25C VCC = +5.0V MIN tsu (H) tsu (L) th (H) th (L) tw (H) tw (L) tw (L) trec Setup time, high or low Dn to CPn Hold time, high or low Dn to CPn CPn pulse width, high or low SDn, RDn pulse width, low Recovery time SDn, RDn to CPn 1 1 1 3 2 2.6 2.4 0 0 1.7 1.7 2.0 2.1 TYP 1.4 1.4 -1.4 -1.4 1.0 1.0 1.3 1.4 Tamb = -40C to +85C VCC = +5.0V 0.5V MIN 2.6 2.4 0 0 2.1 2.1 2.2 2.4 ns ns ns ns ns UNIT
1995 Sep 22
3
Philips Semiconductors
Product specification
Dual D-type flip-flop
74ABT74
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V The shaded areas indicate when the input is permitted to change for predictable output performance
tw(L) VM
Dn
VM tsu(L)
VM th(L) 1/fmax
VM tsu(H)
VM th(H)
SDn VM
CPn
VM tw(H) tPLH
VM
tw(L)
RDn VM tPLH tPHL Qn VM tPHL
tw(L) VM tPHL VM
Qn
VM tPLH
VM tPHL
VM tPLH Qn VM VM
Qn
VM
VM
SF00050 SF00049
Waveform 1. Propagation delay for data to output, data setup time and hold times, and clock width, and maximum clock frequency
Waveform 3. Propagation delay for set and reset to output, set and reset pulse width
INPUT
SDn or RDn
VM trec OUTPUT tPHL
MIN
CPn
VM
SF00051
OUTPUT N same part
tPLH
MIN
Waveform 2. Recovery time for set or reset to clock
tPLH
MAX
tPHL
MAX
tOSLH
tOSHL
SA00381
Waveform 4. Common edge skew
1995 Sep 22
4
Philips Semiconductors
Product specification
Dual D-type flip-flop
74ABT74
TEST CIRCUIT AND WAVEFORMS
VCC 90% NEGATIVE PULSE VIN D.U.T. RT CL RL POSITIVE PULSE VOUT VM 10% tTHL (tF) tTLH (tR) 90% VM tW 90% VM 10% 0V 10% 0V PULSE GENERATOR tTLH (tR) tTHL (tF) AMP (V) tW VM 90% AMP (V)
Test Circuit for Outputs
10%
VM = 1.5V Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS FAMILY Amplitude 74ABT 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns
SH00067
1995 Sep 22
5

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